1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a redundancy circuit capable of replacing defective redundant cells with other redundant cells.
2. Description of the Related Art
Semiconductor devices have become faster and more highly integrated. However, even with the high level of integration, fabrication processes must still provide high integrated circuits yield to reduce costs. In particular, producing economically competitive semiconductor memory devices such as high capacity DRAMs requires high yield together with high integration.
A conventional semiconductor memory device includes many memory cells. However, if one of the memory cells does not operate properly, the semiconductor memory device will not function properly. This problem is a particular concern for highly integrated devices. With higher levels of integration of semiconductor memory devices, the number of memory cells and the probability of defects increase. Such defects are likely to be in more than one memory cell. Defective memory cells thus become one of the main factors in lowering the yield of semiconductor memory devices.
A redundancy circuit improves yield by replacing a defective cell in a semiconductor memory device with a spare or redundant cell that allows the memory device to function properly. Generally, the redundancy circuit connects to a block of redundant memory cells arranged in columns and rows, and selects a set of redundant memory cell from the block to replace a set of memory cells including the defective cell. In particular, the redundancy circuit responds to an address signal corresponding to a defective cell in the main array by accessing a redundant memory cell instead of the defective cell.
U.S. Pat. No. 5,325,334 discloses a known method of replacing defective cells with redundant cells. According to that method, a plurality of fuses within a fuse box array are programmed (i.e., selectively cut or burnt) so that the redundancy circuit responds to a column address signal corresponding to a defective column. Multiple fuse boxes are in the fuse box array to allow repair of multiple defective columns. Each of the fuse boxes includes fuses, which are selectively programmed according to a column address of a corresponding defective column. In response to column address signals corresponding to the defective column, a control circuit, including the fuse box programmed to correspond to the defective column, drives the gate of a redundant column driver to select a redundant column. This redirects access operations to the selected redundant column and thereby replaces defective cells with redundant cells.
However, in the U.S. Pat. No. 5,325,334, when a redundant cell that replaces a detective cell is also defective, the defective redundant cell cannot be replaced by another redundant cell. Thus, the semiconductor memory device is defective and must be discarded. Accordingly, with the known redundancy circuits, redundant memory cells that are defective lower the yield of operable semiconductor memory devices.